Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved

An Overview of Fully On-Chip Inductors

This paper focuses on full integration of passive devices, especially inductors with emphasis on multi-layer stacked (MLS) structures of fully integrated inductors using patterned ground shield (PGS) and fully integrated capacitor. Comparison of different structures is focused on the main electrical parameters of integrated inductors (e.g. inductance L, inductance density LA, quality factor Q, frequency of maximum quality factor F Qmax, self-resonant frequency FSR, and series resistance R DC ) and other non-electrical parameters (e.g. required area, manufacturing process, purpose, etc.) that are equally important during comparison of the structures. Categorization of inductor structures with most significant results that was reported in the last years is proposed according to manufacturing process. Final geometrical and electrical properties of the structure in great manner accounts to the fabrication process of integrated passive device. This work offers an overview and state-of-the-art of the integrated inductors as well as manufacturing processes used for their fabrication. Second purpose of this paper is insertion of the proposed structure from our previous work among the other results reported in the last 7 years. With the proposed solution, one can obtain the highest inductance density L A = 23.59 nH/mm 2 and second highest quality factor Q = 10.09 amongst similar solutions reported in standard technologies that is also suitable competition for integrated inductors manufactured in advanced technology nodes

On-chip Energy Harvesting for Implantable Medical Devices

The paper brings an overview of main challenges in implantable medical devices (IMD) research area, where the main objective of discussion covers wireless power transferring (WPT) systems as the hot topic dedicated to energy harvesting that is still gaining in popularity. The paper is focused on electromagnetic-transfer principle, where full integration of the WPT systems on a chip is taken as the primary goal covering passive transducer and rectifier implementations. The presented research reveals many issues raised from the state of the art solutions. These solutions can or should be detailed investigated in the future research. Therefore, this paper discusses about so far hidden potential of fully integrated WPT systems, where both near-field and far-field approaches are included. Additionally, the discussion is also extended to a principle of power transfer efficiency (PTE) maximization through approaches such as matching and finding the optimal source/load together with rectifying and regulating issues

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulk-driven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 uA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage

On-chip Parametric Test of R-2R Ladder Digital-to-Analog Converter and Its Efficiency

This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder digital-to-analog converter and additional on-chip test hardware was designed in a standard 0.35 μm CMOS technology. For detection of catastrophic and parametric faults considered in different parts of the CUT, two dedicated parametric test methods: oscillation-based test technique and IDDQ monitoring were used. For the operational amplifier, on-chip and off-chip approaches have been used to compare the efficiency of both approaches in covering catastrophic faults that are hard to detect. For respective converter parts, the excellent fault coverage of 94.21% of hard-detectable faults by the proposed parametric tests was achieved

Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved